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- 2015
-
Mark
A 0.6-3.0 GHz 65 nm CMOS Radio Receiver with DS-based A/D-Converting Channel-Select Filters
2015) IEEE European Solid State Circuits Conference, ESSCIRC 2015(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
A 31.25/125MSps Continuous-Time Delta-Sigma ADC with 64/59dB SNDR in 130nm CMOS
2013) NORCHIP Conference, 2013(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
-
Mark
A receiver architecture for devices in wireless body area networks
2012) In IEEE Journal on Emerging and Selected Topics in Circuits and Systems(
- Contribution to journal › Article
- 2011
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to journal › Article
- 2010
-
Mark
Low power multi-band CMOS receiver front-end
2010) PRIME 2010, 6th Conference on Ph.D. Research in Microelectronics & Electronics(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2009
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
A 5.4GHz 90-nm CMOS digitally controlled LC oscillator with 21% tuning range, 1.1MHz resolution, and 180dB FOM
2008) Norchip Conference, 2008(
- Contribution to conference › Paper, not in proceeding